A reconfigurable FEC system based on Reed-Solomon codec for DVB and 802.16 network
Lamia Chaari Fourati, Mohamed Fourati, Nouri Masmoudi, Lotfi Kamoun · 2009
Abstract: This article proposes, a reconfigurable FEC system based on Reed-Solomon codec for DVB and WiMax networks. The proposed architecture implements various programmable primitive polynomials. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrical RS-coder-decoder on FPGAs. The implementation, written in a hardware description language (HDL), is based on an Berlekamp massey, Chain and Formey Algorithms. We have defined an advanced RS encoder-decoder architecture based on parameterization approach which is a key solution for software defined radio (SDR) systems. Our parameterization approach is used in order to implement on FPGA a generic RS coder-decoder for DVB and WiMax networks. IEEE Std. 802.16 specifies that the codec performs a variable number of check symbols in a codeword ( ranges from 0 to 32, inclusive). The value of check symbols are specified for each burst profile by the MAC layer according to cross layer concept.