The evolution of DSP architectures: towards parallelism exploitation
R. Sernec, Matej Zajc, Jurij Franc Tasič · 2005
This paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and have adopted some very sophisticated parallelism extraction techniques, namely very long instruction word (VLIW) and SIMD designs. The intention is to show a development path of digital signal processors (DSP) and focuses on their features that allow parallel processing of algorithms.