A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits
Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori · IEEE Journal of Solid-State Circuits · 2010
A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a$6.4\times 6.5\ {\hbox {mm}}^{2}$die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translation circuits, the processor consumes 342 mW in real-time playback of a full-HD H.264 stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at 1.2 V.