PA7300LC integrates cache for cost/performance
D. Hollenbeck, S. Undy, L. Johnson, Don Weiss, P. Tobin, R. Carlson · 2002
HP continues its development of low cost, high performance processors with an evolution of the PA7100LC which includes 128 kB of on-chip primary cache. It implements the full PA-RISC1.1 functionality including the little-endian, uncacheable memory, and multimedia extensions of the PA7100LC. The PA7300LC connects directly to an optional second level cache of 256 kB to 64 MB using plug-in cards. It also adds the ability to accelerate I/O stores to certain memory locations for greatly improved graphics performance. The cache system consists of on-chip, 2-way, separate instruction and data caches of 64 kB total each, plus the off-chip second level cache. Memory consists of 8 MB to 3.75 GB of standard DRAMs or SIMMs connecting directly to the processor chip, using either a 72 bit or 144 bit data path. The chip is fabricated in 0.5 micron, 4-level metal CMOS and is designed to run at frequencies up to 160 MHz. The PA7300LC exceeds performance levels of previous generation high-end workstations while lowering overall system cost and power consumption.