A novel VLSI architecture for the full search block matching algorithm using systolic array
Sung Bum Pan, Seung Soo Chae, Rae‐Hong Park · 2002
This paper presents a new VLSI architecture of the full search block matching algorithm (FSBMA) using systolic array for motion estimation of moving sequences. The proposed hardware architecture is faster than the conventional ones with lower hardware complexity. It is modeled in very high speed integration circuit hardware description language (VHDL) and simulated to show its functional validity.