Generic ASIC architecture for digital signal processing
S.G. Smith, Ralph W. Morgan, J.G. Payne · 2003
The architectural methodology behind a novel high-level VLSI cell compiler currently under development is described. The tool is aimed specifically at digital signal processing applications, synthesizing powerful arithmetic kernel processors from high-level parameterized schematics. Underlying the tool is a generic pipelined numerical processing architecture, flexible enough in its use of innate parallelism to meet a wide range of throughput requirements with minimal waste of resources. Machines are synthesized using this architecture as a blueprint. To this end, the tool encapsulates the essential knowledge required to assemble a useful set of arithmetic operators over all local and global parametric combinations. Some multiplier instances are illustrated.>