Minimizing pattern count for interconnect test under a ground bounce constraint
Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, R.G. Bennetts · IEEE Design & Test of Computers · 2003
When testing the interconnect structures on a board, test programmers sometimes ask, How can I control the test pattern generation process to avoid ground bounce problems during Extest mode? Those wishing to satisfy a simultaneously-switching-outputs constraint will find several new solutions in this article.