On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing
Tryggve Fossum · 2007
There is increasing interest in chip-level multi-processing, and in this talk I will discuss some the motivations, and some of the challenges in designing such chips. A key component is the on-die interconnect, and we will look at this along with some thoughts on core design, cache architecture, memory bandwidth, power management, error handling, and system scaling.