New design approach for configurable data-path
M. Shiochi, Yasunori Tanaka, M. Enkaku, Taisuke Saigo, Hiroaki R. Suzuki · 2002
The approach described can be used to develop a configurable data-path that has high flexibility, high density, and high performance. It can realize a 32-bit data path array plane in 1.08 mm*1.23 mm using 0.8- mu m CMOS double-metal technology with 6.86 ns arithmetic and logic unit (ALU) operation. By using this design approach for a data path, it is possible to implement a register file and ALU on the same array. The application of the approach to a 32-bit 2901/02 system is discussed.>