FPGA implementation of a FIR filter using residue arithmetic
G. Loonawat, R. Siferd · 2002
Technological advances in VLSI have resulted in more dense and higher speed Field Programmable Gate Arrays (FPGAs), enabling them to be used in a variety of applications. Residue Arithmetic due to its inherent parallelism is ideally suited for implementing digital filters. This paper describes an efficient implementation of a fourth order Finite Impulse Response (FIR) filter combining the advantages of residue arithmetic and FPGAs. The coefficients and input data word width are 12 bits and the coefficients are fully programmable.