Realization of array architectures for video compression algorithms
Yeu-Shen Jehng, Llang-Gee Chen, Tzi‐Dar Chiueh, Thou-Ho Chen · 2003
A practical design technique is presented to realize an array architecture for hierarchical block matching algorithms. A mapping procedure has been applied to derive the array processor from the algorithm. The proposed systolic array is derived to reduce the input/output bandwidth and the hardware cost. This systolic array is configured to be a single-chip of a cascaded architecture to match the requirements of real-time video applications.>