The Case for Analog Circuit Verification
Chris J. Myers, Reid R. Harrison, David John Walter, Nicholas Seegmiller, Scott Little · Electronic Notes in Theoretical Computer Science · 2006
The traditional approach to validate analog circuits is to utilize extensive SPICE-level simulations. The main challenge of this approach is knowing when all important corner cases have been simulated. A new alternative is to utilize formal verification techniques. This paper utilizes a simple example to illustrate the potential flaws of a simulation-only based validation methodology and the potential benefits of formal verification of analog circuits.