An ASIC Array Architecture for the DITPOS Algorithm
Poul Martin Rands Jensen · 1993
this paper we have considered the systematic design of a bit-serial ASIC array architecture for DITPOS. It has been shown that the heterogeneous DITPOS, involving a number of subalgorithms, can be mapped onto a regular array meeting practical I/O scheme and timing requirements. The area consumption of the array is estimated at 125 mm