Synthesis of sequential circuits with clock control to improve testability
K.L. Einspahr, Shashank K. Mehta, Sharad C. Seth · 2002
We propose a new synthesis technique for finite state machines that improves their testability by disabling the clock to a subset of the flip-flops. Distance-matrix results with and without the clock control demonstrate dramatic improvement in the average and worst-case distances between pairs of states. The experimental results using available sequential ATPG tools further verify that the scheme allows significantly shorter tests to be generated with comparable fault coverage.