Precise analog synapse for Kohonen feature maps
P. Heim, Eric A. Vittoz · IEEE Journal of Solid-State Circuits · 1994
A plastic medium-term analog synapse is presented that fulfils the stringent specifications necessary for the Kohonen algorithm. The principle is based on a switched capacitor-like technique implementing a variable time-constant integrator. The memory leakage standard deviation is 2 mV/s for a voltage range of 2 V at room temperature and the learning gain can be varied over two decades. Its differential structure leads to good CMRR, PSRR, and charge injection cancellation. The total synapse area is 1/16 mm/sup 2/ using a 3-/spl mu/m self-aligned contact single-metal CMOS technology. Measurement results of a test chip are also presented.>