High-speed ASIC implementation of AES supporting 128/192/256 bits
Huang Yin, Debiao He, Kang Yong, Fei Xiande · 2009
This paper presented an efficient ASIC implementation of the Advanced Encryption Standard (AES) algorithm encryption/decryption, with key expansion capability. A new way of implementing MixColumns and InvMixColumns transformations using shared logic resources was also explored. The implementation supports 128bits, 192 bits and 256 bits input key. In the hardware architecture, the arithmetic operations in finite field GF(28) can be designed efficiently with combinational logic, and takes advantages of table lookup method.