A scalable memory system design
Kyoung Hwan Kwon, Gab Joong Jeong, Moon Key Lee, Seung Han Ahn · 2002
This paper proposes a new scalable memory architecture with pipeline technique and systolic data flow. We divided entire memory into N/spl times/N sub-memory blocks and placed them onto scalable two-dimensional array that has communication channel of partial binary tree structure. Operating speed is not determined by entire memory size but only by the access time of a single sub-memory block. This architecture is suitable for applications where memory access is random and bursty and high throughput is of major importance. The initial latency is N+3 cycles for N/spl times/N sub-memory block array because of three directional data flow. The 4 k-bit sized prototype with 4/spl times/4 sub-memory block array was designed using 0.8 /spl mu/m two metal CMOS technology. The minimum clock speed is 5.1 ns. The chip size is 35 mm/spl times/3.5 mm.