Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains
Shianling Wu, Laung‐Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang · 2010
This paper presents a new at-speed logic built-in self-test (BIST) architecture using staggered launch-on-shift (LOS) for testing a scan-based BIST design containing asynchronous clock domains. The proposed approach can detect inter-clock-domain structural faults and intra-clock-domain delay and structural faults in the BIST design. This solves the long-standing problem of using the conventional one-hot LOS approach that requires testing one clock domain at a time which causes long test time or using the simultaneous LOS approach that requires adding capture-disabled circuitry to normal functional paths across interacting clock domains which causes fault coverage loss. Given a fixed number of BIST patterns, experimental results showed that the proposed staggered clocking scheme can detect more faults than one-hot clocking and simultaneous clocking.