Bit-serial digital filter architecture using RAM-based delay operators
David Bull, G. Wacey · IEE Proceedings - Circuits Devices and Systems · 1994
Realisations of high-order bit-serial FIR digital filters can be dominated by the shift register stages required for the z-1 operators. This paper presents a new approach to the implementation of bit-serial delay operators based on the use of random access memory in combination with a data transformation process. Together these facilitate the storage and retrieval of serial data in a format compatible with conventional filter requirements. The method is described, an example given and area comparisons made for the cases of FPGA and standard cell ASIC technologies.