Combining IEEE Standard 1149.1 with reduced-pin-count component test
S.F. Oakland · 2002
This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.>