Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics
Phil Moorby, Arturo Salz, Peter L. Flake, Surrendra Dudani · 2003
The SystemVerilog 3.1 language initiative includes the requirement to bring together design, testbench, and assertion-based descriptions into a consistent, backward compatible, evolutionary language standard that achieves determinism and common semantics across the spectrum of design and verification tools. This paper describes the algorithm proposed for the new scheduling semantics that meets these demanding requirements. This algorithm achieves predictable and consistent results across design and verification tools. This proposal has been donated to the Accellera SystemVerilog 3.1 standardization technical committees. Standardization of this new algorithm will extend these benefits to users of other tools. 1.