A VLSI chip set for a massively parallel scientific processor
R. Tripiccione · 2003
The author describes a chip set developed to provide basic building blocks for the APE100 massively parallel SIMD (Single Instruction Multiple Data) processor, designed with ASIC techniques and fabricated in a 1.2 mu m CMOS technology. This chip set contains three devices, which provide three main functions for a SIMD machine, namely the processing element, the controller for the array of processing nodes and the handling of communication among nodes. These functions are respectively provided by the MAD chip (the processing node), the zCpu chip (the controller) and the Commuter chip (communication handler).>