A defect-tolerant and fully testable PLA
Norbert Wehn, Manfred Glesner, K. Caesar, Paul T. Mann, Alan Roth · Design Automation Conference · 1988
The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this type of PLA are presented. >