ARM7 compatible 32-bit RISC processor design and verification
Geun-young Jeong, Ju-sung Park, Hyun-woo Jo, Byung‐Woo Yoon, M.H. Lee · Proceedings. The 9th Russian-Korean International Symposium on Science and Technology, 2005. KORUS 2005. · 2006
The design and verification of a 32-bit general-purpose microprocessor, which is compatible with ARM7 RISC core, is described. In the architectural point of view, the processor has 3-stage pipeline, 6 register banks, 32-bit ALU, and 4-cycle MAC. The core described here was designed by latch base for low power and low complexity. Its functional operation was verified by comparison the results of logic simulation with those of the commercial simulator. Each instruction and its random combinations were tested. The designed core was emulated to check its proper operation for various applications, such as ADPCM, SOLA (voice speed variation), MP3 decoding. Finally it was implemented in 0.5/spl mu/m CMOS process and it carried out successfully those algorithms.