Timing verification for asynchronous design
Ronnie M. Davies, J.V. Woods · 1996
This paper describes a technique for verifying timing conditions inherent in self-timed VLSI designs that make use of the micropipeline design strategy. By checking bundling constraints during simulations, design faults may be de-tected, whilst timing information extracted during the pro-cessing may be used to identify modules requiring optimisa-tion. These analyses may be built around existing simula-tors. 1