A massively parallel VLSI architecture suitable for high-resolution FFT
K. W. Shin, M.-K. Lee · 1991
A new VLSI-oriented array architecture is presented which is suitable for parallel computation of high-resolution fast Fourier transform (FFT). A complete algorithm for computing the FFT on the proposed architecture is also described. With the new index mapping method developed in this work, the architecture offers the following features: (i) a superior time performance of O(N/sup 1/4/) compared to O(N/sup 1/2/) of 2-D mesh array for N-point FFT, (ii) architectural modularity based on two-dimensional subarray modules, (iii) massively parallel processing capability and local communication between processing elements (PEs). Moreover, the adoption of half-butterfly arithmetic (HBA) as the arithmetic function of PE optimizes the performance in terms of reduced data communications between PEs and 100% PE utilization efficiency.>