Cached-code compression for energy minimization in embedded processors
Luca Benini, Alberto Macii, Alberto Nannarelli · 2001
This paper contributes a novel approach for reducing static code size and instruction fetch energy for cache-based core processors running embedded applications. Our irnplemen-tation of the decompression unit guarantees fast and low-energy, on-the-fly instruction decompression at each cache lookup. The decompressor is placed outside the core bound-aries; therefore, processor architecture does not need any modification, making the proposed compression approach suitable to IP-based designs. Viability of our solution is assessed through extensive benchmarking performed on a number of typical embedded programs. 1.