Power estimation at architecture level for embedded systems
H. Mizuno, H. Kobayashi, Takao Onoye, Isao Shirakawa · 2003
This paper proposes a practical approach to the power estimation of an embedded hardware/software codesign system at the architecture level, which intends to optimize the hardware/software configuration from the aspects of power dissipation, hardware cost, and processing performance. A distinctive feature of this approach consists in constructing a precise power estimation model at the architecture level, proper to each hardware component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of the data transfer as well as the functional performance. The power estimation scheme in this model is incorporated into an existing instruction set simulator, so that the power dissipation can be evaluated accurately together with other design factors. This estimation approach enables a set of precise design specifications at the architecture level, which contributes much toward the enhancement of the design ability dedicated to mobile appliances.