Concurrent control of multiple BIT structures
M.A. Breuer, Rajesh K. Gupta, Jung-Cheun Lien · 1988
A generic control graph for activating common built-in test structures is derived and its microprogrammed and hardwired implementations described. Three designs for activating multiple BIT structures concurrently are also presented along with simulation results of area/test time tradeoffs. Two designs for this generic controller are presented. The first design augments the classical microprogrammed controller with some circuitry used for counting. This design is most useful when a microprogrammable controller already exists for normal control operations. The second design is a hardwire unit which efficiently implements the generic controller. A complete circuit-level implementation is described. The controller can be easily made self-testing by modifying an existing register to support signature analysis. In addition, the controller is quite simple and can be incorporated on-chip. >