Unbalanced FIFO sorting for FPGA-based systems
Rui Marcelino, Horácio C. Neto, João M. P. Cardoso · 2009
Sorting is an important operation in a myriad of applications. It can contribute substantially to the overall execution time of an application. Dedicated sorting architectures can be used to accelerate applications and/or to reduce energy consumption. In this paper, we propose an efficient sorting unit aiming at accelerating the sort operation in FPGA-based embedded systems. The proposed sorting unit, named Unbalanced FIFO Merge Sorting Unit, is based on a FIFO merger implementation and is easily scalable to handle different data-set sizes. We show results of the proposed sorting unit when isolated and when integrated in a software/hardware solution. When using a Xilinx Virtex-5 SX50T FPGA device, the logic resources for a 32 K-word machine is lower than 1%, and the block RAM usage is about 22%. When compared to a quicksort pure software implementation, our Sorting Unit provides speed-ups from 1.2x to 50x and about 20x when isolated and when integrated in a software/hardware solution, respectively.