Integrating of Verilog-HDL and VHDL languages in the SMASH/sup TM/ mixed-signal multi-level simulator
P. Sauge, Ghislaine Thuau · 2002
This paper describes the integration of hardware description languages (Verilog-HDL and VHDL) within the SMASH/sup TM/ mixed-signal multi-level simulator. A solution for integrating high levels of abstraction within a mixed-signal simulation environment is presented. This solution uses concurrency of processes, which is inherent to circuit descriptions. The technique uses transcompilation, where Verilog-HDL and VHDL processes are mapped to C language regular processes. These processes are compiled, to create executable code which is dynamically linked to the simulator kernel. Handling of concurrency is achieved in an elegant way, through abstract events, which are sequenced by the simulation kernel.