Parity-scan design to reduce the cost of test application
Hideo Fujiwara, A. Yamamoto · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993
Points out that scan design approach is representative of those techniques that can reduce the cost of test generation for sequential circuits. However, the length of a test sequence for the scan design approach can grow quite large due to the scan operation shifting the values into the scan chain, which makes the cost of test application large. A design-for-testability approach called parity-scan design which can reduce the cost of test application as well as the cost of test generation for sequential circuits is discussed. The parity-scan design approach is a combination of scan technique and parity testing. Two types of parity-scan designs, preparity and postparity scan design, are presented. Experiments on ISCAS89 circuits show that as high as 91.2% (91.1%) test length reduction and 32.4% (27.0%) average reduction can be obtained for preparity (postparity) scan design under the single scan chain approach. More reduction can be achieved by applying a multiple scan chain technique.>