Logic circuit extraction for bridging fault equivalence identification in CMOS ICs
M. Simoes, I.C. Teixeira, João Paulo Teixeira · 2002
A new methodology for test preparation, at gate level, is introduced. Realistic bridging faults between logical nodes are used as a fault model. The methodology requires logic circuit extraction, from the transistor circuit netlist: hence, a new logic extractor for static CMOS designs, tabloid, is presented. Preliminary results on logic extraction, and bridging fault equivalence identification are presented.>