High-performance floating-point VLSI architecture of a lifting-based wavelet processor
Andre Guntoro, Massoud Momeni, Hans-Peter Keil, Manfred Glesner · 2008
In this paper, we propose a high-performance lifting-based wavelet processor that can perform various forward and inverse DWTs. Our architecture is based on NxM PEs which can perform either prediction or update on a continuous data stream in every clock cycle. In order to improve the accuracy, floating-point arithmetics are used to compute the transformation. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. For the 32-bit implementation, the estimated area of the proposed wavelet processor with 2times8 PEs in a 0.18-mum technology is 4.8 mm square and the estimated operating frequency is 308 MHz.