A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes
Se-Joong Lee, Kwanho Kim, Hye Jung Kim, Namjun Cho, Hoi‐Jun Yoo · 2006
An on-chip interconnect is implemented with 3Gbps/wire bandwidth performance with 8:1 serialization scheme. Such high-speed serialization is achieved using a novel serialization scheme, wave-front-train. In order to apply such high-speed link technique to network-on-chip channels, three adaptive control schemes are used: supply voltage dependent reference voltage control, phase compensation scheme with self-calibrating function, and adaptive bandwidth control. The chip is fabricated using 0.18/spl mu/m CMOS technology.