A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures
Balasubramanian Sethuraman, Ranga R. Vemuri · 2007
Networks-on-chip (NoC) is an emerging style of system design introduced to overcome the communication and the performance bottlenecks of a shared-bus design. Away from the traditional NoC mesh design, multi local port router (MLPR) has been introduced as design alternative to improve the bandwidth, reduce the network area (36% average area savings) and eventually, improve the overall performance of the NoC system. In this research, we present a fast mapping tool (cMap) for generating NoC architectures using MLPRs. The algorithm exploits the advantages offered by MLPRs and starts with a minimum dimension mesh. After an initial bandwidth-communication-cost based nearest-neighbor placement, it uses a force-directed approach to iteratively expand the mesh, as the cost gets reduced. The algorithm introduces the concept of folding to improve the NoC design. Unlike the earlier exhaustive-search based optiMap algorithm, cMap can handle any size of the task graph, producing near-optimal results (average cost difference between 3% and 10%,) in a couple of seconds. We experiment with a rich set of 22 benchmarks and report the results