Optimal granularity of test generation in a distributed system
Hideo Fujiwara, Tomoo Inoue · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1990
The problem of test generation for logic circuits is known to be NP-hard, hence it is very difficult to speed up the test-generation process due to its backtracking mechanism. An approach to parallel processing of test generation for logic circuits in a loosely coupled distributed network of general-purpose computers is presented, and the effects of allocating target faults to processors, the optimal granularity (grain size of target faults), and the speed up ratio of the multiple processor system compared with a single processor system are analyzed.>