Hardware/software co-design of a fuzzy RISC processor
Valentina Salapura, Michael K. Gschwind · 1998
In this paper, we show how hardware/software co-evaluation can be applied to instruction set definition. As a case study, we show the definition and evaluation of in-struction set extensions for fuzzy processing. These in-structions are based on the use of subword parallelism to fully exploit the processor’s resources by processing mul-tiple data streams in parallel. The proposed instructions are evaluated in software and hardware to gain a balanced view of the costs and benefits of each instruction. We have found that a simple instruction optimized to perform fuzzy rule evaluation offers the most benefit to improve fuzzy pro-cessing performance. The instruction set extensions are added to a RISC pro-cessor core based on the MIPS instruction set architecture. The core has been described in VHDL so that hardware implementations can be generated using logic synthesis. 1