Dataflow models for shared memory access latency analysis
Jan Staschulat, Marco J.G. Bekooij · 2009
Performance analysis of applications in multi-core platforms is challenging because of temporal interference while accessing shared resources. Especially, memory arbiters introduce a non-constant delay which significantly influences the execution time of a task. In this paper, we selected a priority-based budget scheduler as memory arbiter which bounds temporal interference by construction and is well suited for bursty service provision. While existing performance analysis approaches assume a constant memory access latency leading to high overestimation, we propose in this paper a conservative data flow model for this scheduler, in which the history of memory accesses is considered.