Non-conventional faults in BiCMOS digital circuits
C. Siyad, Edward J. McCluskey · 1992
Resistive “shorts“ {unplanned connections) within BiCMOS gates are studied. A simple model to determine the output of a faulty BiCMOS gate is derived. Defective BiCMOS NAND gates with various resistive shorts are simulated using SPICE. Two types of new faults are identified. These faults, which may escape functional tests, are explained through the simple model. Simulation results show that current monitoring is an effective way to detect these faults.