Hardware Implementation of Improved Montgomery Modular Multiplication Algorithm
Jia Hong Zhang, Xiong Tinggang, Xiangyan Fang · 2009
This paper describes a hardware implementation of modular multiplication coprocessor for both RSA and ECC Cryptosystems. Using a self-improvement Montgomery modular multiplication algorithm, the coprocessor completes a modular multiplication with less clock cycles under the equivalent circumstance of the other designs. This modular multiplier can deal with variable operand lengths, from 128 to 2048. When adopting 64 bits multiplier, it can work at the frequency of 100 MHz targeted to Virtex II XC2V250, and executes 256 bits EC point multiplication, with throughput 172 k bit/s and 1024 bits RSA decryption (using CRT), with throughput 483 k bit/s.