A new decoding scheme and erase sequence for 5 V only sector erasable flash memory
T. Nakayama, S. Kobayashi, Y. Miyawaki, T. Futatsuya, Y. Terada, N. Ajika, Tatsuhiko Yoshihara · 2003
The authors describe a decoding scheme and erase sequence for a 5-V-only sector-erasable flash memory. A source line decoder eliminates the erase disturb problem and lowers the power consumption. The maximum switching voltage is reduced to 10 V, which makes possible a tight word line pitch for a 64-Mb flash memory. Narrow threshold voltage distribution of erased memory cells is obtained by programming after erase.>