Design of an DFE equalizer ASIC chip using the MMA algorithm
Daekyo Shin, Sung Jun Hwang, Myung Hoon Sunwoo · 2002
This paper proposes a DFE (decision feedback equalizer) equalizer ASIC chip using the multi-modulus algorithm (MMA). We believe that it is the first effort to combine the DFE structure and the MMA algorithm. The proposed equalizer has been designed for 64/256 QAM demodulations. The existing MMA equalizer uses two transversal filters while the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps. We have used the 0.35 /spl mu/m standard cell library. The fabricated equalizer ASIC chip operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The total number of the gates is about 160,000.