Prefix Parallel Adder Virtual Implementation in Reversible Logic
David Y. Feinstein, Mitchell Aaron Thornton, Vivek Nair · 2007
This paper demonstrates a simplified approach for reversible logic synthesis based on direct translation of the circuit VHDL description into virtual Fredkin gates. We investigate the size and speed of such a reversible logic implementation of the Brent-Kung Parallel Prefix Adder (PPA) in comparison to a standard logic implementation. Using the Altera Corporation's Quartic II synthesis and simulation tool, we show that our virtual reversible logic implementation follows the O(log2n) delay and O(n) cost of the standard logic implementation.