On robust two-pattern testing of one-dimensional CMOS iterative logic arrays
Dimitris Gizopoulos, Antonis Paschalis, Dimitris Nikolos, Constantine Halatsis · International Journal of Electronics · 1999
In this paper a graph model and a method to construct robust (for the first time in open literature) as well as non-robust two-pattern tests for one-dimensional iterative logic arrays (ILAs) are presented. Exploring the graph structure we can find two-pattern tests that can be applied with a constant or linear number of test vectors to all the ILA cells. Such tests are subsequently characterized as robust or non-robust two-pattern tests.