REALIZATION AND EXTENSIONS OF USER PROGRAMMABLE, SINGLE-LEVEL, DOUBLE-THRESHOLD GENERALIZED PERCEPTRON
Devrim Yılmaz Aksin, Sualp Aras, İzzet Cem Göknar · DergiPark (Istanbul University) · 2011
The implementation of a perceptron that can classify data separable by two parallel hyper-planes or equivalentlyof a Single-Level TL-XOR gate is proposed using 10 MOS transistors and 2 capacitors. The functional subblockdecomposition of the Perceptron with two separating hyper-planes, its CMOS implementation explainingthe operation of each sub-block and simulation results, obtained using the SpectreS simulator and AMS 0.8mmCMOS double-poly double-metal technology parameters are presented. A brief outline of the two level CTLrealization and its comparison with the new implementation are given as far as their transistor count,programmability and total delay are concerned.Key Words: Perceptron, Neural Networks, Threshold Logic, XOR Gate