A programmable signal processing architecture
J. Glass · 2005
A processor architecture is described that permits a substantial increase in throughput from that obtained with more conventional designs. The subject processor is structured with parallel FFT and non FFT arithmetic units that can operate simultaneously. The nonFFT portion, driven from a horizontal µ code word, has parallel ALU's that allow a high degree of efficiency for many algorithms. The system is designed to be extremely efficient for array-oriented operations, and can be used with a high-level programming language that is translated by an off-line macroassembler into instructions used by the sequence control portion of the processor. The processor has been built and is currently operating within a radar system.