Low power architecture of running 3-D wavelet transform for medical imaging application
Bijit Kumar Das, Swapna Banerjee · 2002
In this paper a real-time 3-D DWT algorithm and its architecture realization is proposed. Reduced buffer and low wait-time are the salient features which makes it fit for bidirectional videoconferencing applications mostly in real-time biomedical applications. The proposed algorithm updates the coefficients in the temporal direction with every two new frames. In the architectural implementation, the memory requirement is minimal due to low buffering requirement. The reduced hardware complexity and 100% hardware utilization is ensured in this design. Time area product for the spatial DWT is 1.5 at. This architecture implemented on 0.25 /spl mu/ BiCMOS technology. At a operating frequency of 100 MHz the power consumption is appreciably lower compared to those reported.