A programmable security processor for cryptography algorithms
Lin Han, Jun Shu Han, Xiaoyang Zeng, Ronghua Lu, Jia Zhao · 2008
A novel programmable security processor for cryptography algorithms is presented in this paper. The 16-bit length RISC-like instruction set and 3-stage pipeline provide low code density, low hardware cost and low power consumption. Parallel on-chip lookup tables are integrated to obtain satisfactory performance of cryptographic processing. Chinese wireless local area network block cipher standard-SMS4 and NIST encryption standard-AES are implemented in this processor, and it is the first implementation of SMS4 based on a domain specific programmable processor. To resist external attack on memories, a method for secure storage of round key is also proposed.