Evaluating schedulers for multimedia processing on buffer-constrained SoC platforms
Alexander Maxiaguine, Simon Künzli, Lothar Thiele, Samarjit Chakraborty · IEEE Design & Test of Computers · 2004
Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.